Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, hydroxyl, aldehyde, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

A method and an apparatus for filling a gap by using an atomic layer deposition (ALD) method are provided. The method includes forming a first reaction inhibition layer on a side wall of the gap; forming a first precursor layer by adsorbing a first reactant into a bottom of the gap and the side wall of the gap around the bottom of the gap; and forming a first atomic layer on the bottom of the gap and the side wall of the gap around the bottom of the gap by adsorbing a second reactant into the first precursor layer. The forming of the first reaction inhibition layer may include adsorbing a first reaction inhibitor into the side wall of the gap; and forming a second reaction inhibitor by removing a specific ligand from the first reaction inhibitor.

Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.

There is provided a technique that includes: loading an m-th substrate into a process chamber, wherein m is an integer less than n; forming a film on the m-th substrate by heating the m-th substrate in the process chamber; unloading the m-th substrate from the process chamber; waiting for a predetermined time in the process chamber, in a state where the substrates are not present in the process chamber, after the act of unloading; loading a next substrate, which is one of the n substrates to be processed next, into the process chamber, after the act of waiting; and forming a film on the next substrate by heating the next substrate in the process chamber.

A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.

A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.

Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contains a different metal selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

Provided is a vacuum processing method capable of preventing particles from adhering to a wafer due to a titanium (Ti)-based reaction product. The vacuum processing method is applicable to a plasma processing apparatus including: a sample stage disposed in a processing chamber inside a vacuum container, on which a wafer having a titanium (Ti)-containing film is placed; a coil supplied with a radio frequency power for forming plasma in the processing chamber; and a heating device that emits an electromagnetic wave for heating the wafer placed on an upper surface of the sample stage. The vacuum processing method includes a step of etching the titanium (Ti)-containing film, and a step of cleaning an inside of the processing chamber by using a mixed gas of nitrogen trifluoride (NF.sub.3) gas, argon gas, and a chlorine gas.

A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.