H01L21/02189

TRIPLE STRUCTURE CELL AND ELEMENT INCLUDING THE SAME
20220336595 · 2022-10-20 ·

Disclosed is a triple structure cell and an element including the same. The ferroelectric cell of the triple structure includes a polarizable material layer, a top dielectric layer disposed on the polarizable material layer, and a bottom dielectric layer disposed under the polarizable material layer.

Method of manufacturing semiconductor device
11476339 · 2022-10-18 · ·

To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

METHOD AND APPARATUS FOR FILLING GAP USING ATOMIC LAYER DEPOSITION

A method and an apparatus for filling a gap by using an atomic layer deposition (ALD) method are provided. The method includes forming a first reaction inhibition layer on a side wall of the gap; forming a first precursor layer by adsorbing a first reactant into a bottom of the gap and the side wall of the gap around the bottom of the gap; and forming a first atomic layer on the bottom of the gap and the side wall of the gap around the bottom of the gap by adsorbing a second reactant into the first precursor layer. The forming of the first reaction inhibition layer may include adsorbing a first reaction inhibitor into the side wall of the gap; and forming a second reaction inhibitor by removing a specific ligand from the first reaction inhibitor.

PLASMA PROCESSING WITH TUNABLE NITRIDATION
20230127138 · 2023-04-27 ·

In an embodiment, a method for nitriding a substrate is provided. The method includes flowing a nitrogen-containing source and a carrier gas into a plasma processing source coupled to a chamber such that a flow rate of the nitrogen-containing source is from about 3% to 20% of a flow rate of the carrier gas; generating an inductively-coupled plasma (ICP) in the plasma processing source by operating an ICP source, the ICP comprising a radical species formed from the nitrogen-containing source, the carrier gas, or both; and nitriding the substrate within the chamber, wherein nitriding includes operating a heat source within the chamber at a temperature from about 150° C. to about 650° C. to heat the substrate; maintaining a pressure of the chamber from about 50 mTorr to about 2 Torr; introducing the ICP to the chamber; and adjusting a characteristic of the substrate by exposing the substrate to the radical species.

Layer stack for display applications

Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.

Source/drain feature separation structure

A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Group 5 metal compound for thin film deposition and method of forming group 5 metal-containing thin film using same
11634441 · 2023-04-25 · ·

A group 5 metal compound according to an embodiment of the present disclosure is represented by any one of the following <Chemical Formula 1> and <Chemical Formula 2>: ##STR00001## In <Chemical Formula 1> and <Chemical Formula 2>, M is any one selected from group 5 metal elements, n is any one selected from an integer of 1 to 5, R.sub.1 is any one selected from a linear alkyl group having 3 to 6 carbon atoms and a branched alkyl group having 3 to 6 carbon atoms, and R.sub.2 and R.sub.3 are each independently any one selected from hydrogen, a linear alkyl group having 1 to 4 carbon atoms, and a branched alkyl group having 1 to 4 carbon atoms.

Semiconductor memory device and method of fabricating the same

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.

SELECTIVE DEPOSITION OF METAL OXIDE BY PULSED CHEMICAL VAPOR DEPOSITION

Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contains a different metal selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.