Exemplary processing methods include forming a nucleation layer on a substrate. The nucleation layer may be formed by physical vapor deposition (PVD), and the physical vapor deposition may be characterized by a deposition temperature of greater than or about 700° C. The methods may further include forming a patterned mask layer on the nucleation layer. The patterned mask layer may include openings that expose portions of the nucleation layer. Gallium-and-nitrogen-containing regions may be formed on the exposed portions of the nucleation layer. In additional embodiments, the nucleation layer may include a first and second portion separated by an interlayer that stop the propagation of at least some dislocations in the nucleation layer.

Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a <hk0>, <h00>, or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Described herein is a technique capable of improving the productivity of manufacturing of a semiconductor device in a method of processing a film by repeating different processes. A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process vessel; (b) forming a first layer by supplying a first gas into the process vessel by a gas supply unit while maintaining the substrate at a first temperature by a temperature control unit; and (c) forming a second layer different from the first layer by supplying a second gas different from the first gas into the process vessel by the gas supply unit while maintaining the substrate at a second temperature different from the second temperature by the temperature control unit.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A semiconductor structure includes a substrate and a gate stack structure located on the substrate. The gate stack structure includes: a high-K dielectric layer, a first barrier layer in contact with the high-K dielectric layer, a work function layer located on a side of the high-K dielectric layer away from the substrate, and a gate electrode layer located on a side of the work function layer away from the substrate. The first barrier layer contains the same metal element as the high-K dielectric layer.

An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO.sub.2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.