A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.

In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

Methods of forming a crystalline strontium titanate layer may include providing a substrate with a crystal enhancement surface (e.g., Pt), depositing strontium titanate by atomic layer deposition, and conducting a post-deposition anneal to crystallize the strontium titanate. Large single crystal domains may be formed, laterally extending greater distances than the thickness of the strontium titanate and demonstrating greater ordering than the underlying crystal enhancement surface provided to initiate ALD. Functional oxides, particularly perovskite complex oxides, can be heteroepitaxially deposited over the crystallized STO.

A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

An atomic layer deposition apparatus for forming an atomic layer on a flexible substrate, the apparatus including an unwinding chamber having an unwinding roll for unwinding the flexible substrate, a winding chamber having a winding roll for winding the flexible substrate on which the atomic layer is formed, a plurality of reaction chambers provided between the unwinding chamber and the winding chamber so that the flexible substrate can pass therethrough, a first supply part for storing a gas containing a first precursor, a first supply pipe connected to the first supply part, a second supply part for storing a purge gas, a second supply pipe connected to the second supply part, a third supply part for storing a gas containing a second precursor, a third supply pipe connected to the third supply part, and an exhaust pipe connected to the plurality of reaction chambers.

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.

The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.

Provided is a method for forming a ferroelectric film of a metal oxide having a fluorite-type structure at a low temperature of lower than 300° C., and a ferroelectric film obtained at a low temperature. The present invention provides a production method of a ferroelectric film comprising a crystalline metal oxide having a fluorite-type structure of an orthorhombic crystal phase, which comprises using a film sputtering method comprising sputtering a target at a substrate temperature of lower than 300° C., to deposit on the substrate a film of a metal oxide which is capable of having a fluorite-type structure of an orthorhombic crystal phase, and having a subsequent thermal history of said film of lower than 300° C.; or applying an electric field to said film after said deposition or after said thermal history of lower than 300° C. Also provided are the ferroelectric film, which is formed on an organic substrate, glass, or metal substrate, which can be used only at low temperatures, and a ferroelectric element and a ferroelectric functional element or device using the ferroelectric film.