H01L21/02277

Cleaning method, method of manufacturing semiconductor device, substrate processing apparatus, and recording medium

There is provided a cleaning technique that includes supplying a hydrogen fluoride gas into a process vessel, in which a process of forming an oxide film containing at least one of carbon and nitrogen on a substrate has been performed, to remove a deposit containing at least one of carbon and nitrogen adhered to an interior of the process vessel, wherein the act of supplying the hydrogen fluoride gas is performed under a condition in which an etching rate of the deposit adhered to the interior of the process vessel is higher than an etching rate of a quartz member in the process vessel.

Method of manufacturing semiconductor device, recording medium, and substrate processing method

A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.

Semiconductor Device Gate Spacer Structures and Methods Thereof
20210050431 · 2021-02-18 ·

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

METHOD OF SELECTIVE DEPOSITION FOR FORMING FULLY SELF-ALIGNED VIAS
20210074584 · 2021-03-11 ·

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

METHOD FOR FORMING A LOW-K SPACER

The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.

GATE CAPPING LAYERS OF SEMICONDUCTOR DEVICES
20200388693 · 2020-12-10 ·

A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

Method of selective deposition for forming fully self-aligned vias
10847363 · 2020-11-24 · ·

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

COBALT PRECURSOR AND METHODS FOR MANUFACTURE USING THE SAME

The inventive concept relates to a cobalt precursor, a method for manufacturing a cobalt-containing layer using the same, and a method for manufacturing a semiconductor device using the same. More particularly, the cobalt precursor of the inventive concept includes at least one compound selected from the group consisting of a compound of Formula 1 and a compound of Formula 2.

METHOD FOR PRODUCING SILICON NITRIDE FILM

A method for preparing a silicon nitride film with a high deposition rate and a reduced damage to the substrate and/or the underlying layer formed under the silicon nitride film. The method for preparing a silicon nitride film contains the steps of irradiating a nitride with an ultraviolet light, and contacting the nitride irradiated with the ultraviolet light and a hydrogenated cyclic silane represented by a general formula Si.sub.nH.sub.2n, wherein n is 5, 6, or 7.

Semiconductor device gate spacer structures and methods thereof

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.