Patent classifications
H01L21/02326
Field effect transistor
A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.
Semiconductor device with electrodes over oxide semiconductor
Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.
Semiconductor device and method for manufacturing the same
A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND RECORDING MEDIUM
To reduce a hydroxy group in a silicon oxide film formed at a low temperature and obtain a silicon oxide film with an excellent film quality, (a) accommodating a substrate on a surface of which a silicon oxide film formed at a processing temperature of 300° C. or lower is formed in a processing container, (b) plasma-exciting a hydrogen gas, and a step of supplying hydrogen active species generated in (b) to the substrate are performed.
Silicon rich nitride layer between a plurality of semiconductor layers
According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENT
Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor includes: providing a substrate; forming a polysilicon layer on the substrate, a surface, away from the substrate, of the polysilicon layer having a native oxide; and performing a nitriding treatment to the native oxide, to nitrogenize the native oxide into a silicon oxynitride layer. The native oxide is nitrogenized into the silicon oxynitride layer.
Stress Modulation Using STI Capping Layer for Reducing Fin Bending
A method includes etching a semiconductor substrate to form a semiconductor strip and a recess, with a sidewall of the semiconductor strip being exposed to the recess, depositing a dielectric layer into the recess, and depositing a capping layer over the dielectric layer. The capping layer extends into the recess, and comprises silicon oxynitride. The method further includes filling remaining portions of the recess with dielectric materials, performing an anneal process to remove nitrogen from the capping layer, and recessing the dielectric materials, the capping layer, and the dielectric layer. The remaining portions of the dielectric materials, the capping layer, and the dielectric layer form an isolation region. A portion of the semiconductor strip protrudes higher than a top surface of the isolation region to form a semiconductor fin.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR MEMORY DEVICE MANUFACTURING METHOD, SEMICONDUCTOR MEMORY DEVICE, AND SUBSTRATE TREATMENT APPARATUS
A semiconductor device manufacturing method of embodiments includes: forming an aluminum nitride film; forming an aluminum hydroxide film containing diaspore-type aluminum hydroxide by performing treatment in a fluid containing water to the aluminum nitride film; and forming an aluminum oxide film containing α-type aluminum oxide by performing heat treatment to the aluminum hydroxide film at a temperature equal to or more than 500° C. and equal to or less than 800° C.
COMPOSITIONS AND METHODS USING SAME FOR DEPOSITION OF SILICON-CONTAINING FILMS
Described herein are compositions and methods using same for forming a silicon-containing film or material such as without limitation a silicon oxide, silicon nitride, silicon oxynitride, a carbon-doped silicon nitride, or a carbon-doped silicon oxide film in a semiconductor deposition process, such as without limitation, a plasma enhanced atomic layer deposition of silicon-containing film.