A semiconductor device includes: a semiconductor film including a Schottky junction region and an Ohmic junction region; a Schottky electrode arranged on the Schottky junction region; and an Ohmic electrode arranged on the Ohmic junction region, the Schottky junction region having a first dislocation density, the Ohmic junction region having a second dislocation region, and the first dislocation density being smaller than the second dislocation density.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

A method for manufacturing a semiconductor element includes providing, on a surface of a substrate 11, a mask 12 which has an opening 12a and in which a peripheral upper surface region of the opening is processed to have a predetermined structure, and epitaxially growing a semiconductor from the surface of the substrate exposed from the opening to the top of the peripheral upper surface region to fabricate a semiconductor element having a semiconductor layer 13 with the predetermined structure transferred thereon. In one example, the predetermined structure is due to a shape having a difference in level. In another example, the predetermined structure is due to a selectively arranged element, and the transferred element moves into the semiconductor layer.

A method for selectively depositing an amorphous silicon film on a substrate comprising a metallic nitride surface and a metallic oxide surface is disclosed. The method may include; providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, contacting the substrate with silicon iodide precursor, and selectively depositing the amorphous silicon film on the metallic nitride surface relative to the metallic oxide surface. Semiconductor device structures including an amorphous silicon film deposited by selective deposition methods are also disclosed.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.

Embodiments of the invention relate to a method for fabricating a semiconductor structure comprising a semiconductor material, and a semiconductor substrate fabricated from the method. The method can include a step of providing a template structure. The template structure can comprise an opening, a cavity and a seed structure. The seed structure can comprise a seed material and a seed surface. An inner surface of the template structure can comprise at least one metallic surface area comprising a metallic material. The embodied method further comprises a step of growing the semiconductor structure within the cavity of the template structure from the seed surface along the metallic surface area.

A topology-selective deposition method is disclosed. An exemplary method includes providing an inhibition agent comprising a first nitrogen-containing gas, providing a deposition promotion agent comprising a second nitrogen-containing gas to form an activated surface on one or more of a top surface, a bottom surface, and a sidewall surface relative to one or more of the other of the top surface, the bottom surface, and the sidewall surface, and providing a precursor to react with the activated surface to thereby selectively form material comprising a nitride on the activated surface.

An epitaxial lateral overgrowth (ELO) of a III-nitride layer is used to cover a growth restrict mask deposited on a substrate, wherein the III-nitride ELO layer is grown with a low V/III ratio of less than 500 resulting in high-speed lateral growth as compared to low-speed vertical growth. The III-nitride ELO layer contains a large amount of impurities, over 1 × 10.sup.18 cm.sup.-3, which result in the III-nitride ELO layer comprising a coloring layer. The coloring layer absorbs light from an active region due to the large amount of impurities. When a bar of device layers is removed from the substrate, at least a portion of the coloring layer is removed from the bar. The elimination of the coloring layer reduces absorption losses, which makes the device characteristics improve.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

Epitaxial growth of materials, and related systems and articles, are generally described.