A method for preparing a self-supporting substrate includes: preparing a thin film base structure including a first substrate layer, a thin film layer and a second substrate layer stacked in sequence; removing the first substrate layer from the thin film layer; continuing to grow a material the same as that of the thin film layer on a side of the thin film layer far away from the second substrate layer to prepare a thick film layer; and removing the second substrate layer from the thick film layer and remaining the thick film layer. In the method, a thin film may be grown on a substrate that has a larger diameter, and a thinness of the thin film will not cause the thin film and/or the substrate to crack. Therefore, a thin film that has a large diameter may be obtained so as to obtain a large-sized self-supporting thick film substrate.

Described are light emitting diode (LED) devices having patterned substrates and methods for effectively growing epitaxial III-nitride layers on them. A nucleation layer, comprising a III-nitride material, is grown on a substrate before any patterning takes place. The nucleation layer results in growth of smooth coalesced III-nitride layers over the patterns.

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface.

A method includes etching a first and a second semiconductor fin to form a first and a second recesses, epitaxially growing an n-type source/drain region comprising a first portion and a second portion from the first and the second recesses, and a first middle portion in between and having a concave top surface. A first contact opening is formed extending into the n-type source/drain region and having a first V-shaped bottom. The method further includes etching a third and a fourth semiconductor fin to form a third and a fourth recesses, and forming a p-type source/drain region including a third portion and a third portion grown from the third and the fourth recesses, and a second middle portion in between and having a convex top surface. A second contact opening is formed and has a second V-shaped bottom, with a tip of the second V-shaped bottom being downwardly pointing.

A semiconductor device comprising: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.

A method of manufacturing a semiconductor substrate includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a first portion of a second semiconductor layer on the first semiconductor layer and the metallic material layer, removing the metallic material layer under the first portion of the second semiconductor layer by dipping the substrate in a solution, forming a second portion of the second semiconductor layer on the first portion of the second semiconductor layer, and forming a cavity entirely through a portion of the first semiconductor layer located under where the metallic material layer was removed.