Patent classifications
H01L21/0265
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.
Methods Of Cooling Semiconductor Devices
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
MERGED SOURCE/DRAIN FEATURES
The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Epitaxial III-N nanoribbon structures for device fabrication
A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.
INDIUM-GALLIUM-NITRIDE STRUCTURES AND DEVICES
InGaN layers characterized by an in-plane lattice parameter within a range from 3.19 Å to 3.50 Å are disclosed. The InGaN layers are grown by coalescing InGaN grown on a plurality of GaN seed regions. The InGaN layers can be used to fabricate optical and electronic devices for use in light sources for illumination and display applications.
Semiconductor device having a planar III-N semiconductor layer and fabrication method
A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).
METHOD FOR PRODUCING A NITRIDE LAYER
A method for producing at least one nitride layer includes providing a stack having a plurality of pillars extending from a substrate of the stack. Each pillar includes at least a crystalline section and a summit having a summit surface area The method also includes growing by epitaxy a crystallite from the summit of some the plurality of pillars and continuing the epitaxial growth of the crystallites until the crystallites supported by the pillars coalesce. The plurality of pillars includes at least one retention pillar and separation pillars. The pillars are configured so that once the nitride layer is formed, the at least one retention pillar retains the nitride layer and some of the separation pillars can fracture.
FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions
A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface.
Surface-emitting laser and method for manufacturing surface-emitting laser
A method for manufacturing a surface emitting laser made of a group-III nitride semiconductor by an MOVPE method includes: (a) growing a first cladding layer of a first conductive type on a substrate; (b) growing a first optical guide layer of the first conductive type on the first cladding layer; (c) forming holes having a two-dimensional periodicity in a plane parallel to the first optical guide layer, in the first optical guide layer by etching; (d) supplying a gas containing a group-III material and a nitrogen source and performing growth to form recessed portions having a facet of a predetermined plane direction above openings of the holes, thereby closing the openings of the holes; and (e) planarizing the recessed portions by mass transport, after the openings of the holes have been closed, wherein after the planarizing at least one side surface of the holes is a {10-10} facet.
Light Emitting Diode (LED) Devices With Nucleation Layer
Described are light emitting diode (LED) devices having patterned substrates and methods for effectively growing epitaxial III-nitride layers on them. A nucleation layer, comprising a III-nitride material, is grown on a substrate before any patterning takes place. The nucleation layer results in growth of smooth coalesced III-nitride layers over the patterns.