A layer on a substrate is laser annealed by pulses in a plurality of laser beams formed into a uniform line beam. The laser beams are partitioned into a first set of beams and a second set of beams. The second set of beams is incident onto the layer from a smaller range of angles than all of the beams combined. Pulses in the beams are synchronized such that pulses in the first set of beams are incident on the layer before pulses in the second set of beams. Pulses in the first set of beams melt the layer and pulses in the second set of beams sustain melting.

Provided are a variable pulse width flat-top laser device and an operation method therefor. A variable pulse width flat-top laser device includes a light source unit including first and second laser light sources driven at different times to respectively emit pulse-type first and second laser beams, a beam shaping unit configured to shape the first and second laser beams emitted from the light source unit into flat-top laser beams, a combination/split unit located between the light source unit and the beam shaping unit, and including a first beam combination/split unit configured to combine optical paths of the first and second laser beams and split a combined optical path into at least two optical paths so that the split at least two optical paths are directed to different regions of an incident surface of the beam shaping unit, and an imaging optical system configured to time-sequentially overlay the flat-top laser beams shaped by the beam shaping unit on a target object to form an image.

A laser processing device and a laser processing method that are capable of forming a high-quality semiconductor film are provided. An ELA device (excimer laser annealing device) (1) includes a laser oscillator (10) that generates laser light for forming a polysilicon film by irradiating an amorphous silicon film over a substrate to be processed with the laser light, a pulse measuring instrument (100) for detecting first partial light and second partial light contained in the laser light, and a monitoring device (60) for comparing a detection result of the first partial light with a detection result of the second partial light.

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

A method for manufacturing a structured substrate provided with a trap-rich layer whereon rests a stack consisting of an insulating layer and of a layer of single-crystal material, includes forming an amorphous silicon layer on a front face of a silicon substrate and heat treating intended to convert the amorphous silicon layer into a trap-rich layer made of single-crystal silicon grains. The heat treatment conditions in terms of duration and of temperature are adjusted to limit the grains to a size less than 200 nm. The method also includes overlapping the trap-rich layer with an insulating layer and a layer of single-crystal material.

In one aspect, a method of processing a semiconductor substrate is disclosed, which comprises incorporating at least one dopant in a semiconductor substrate so as to generate a doped polyphase surface layer on a light-trapping surface, and optically annealing the surface layer via exposure to a plurality of laser pulses having a pulsewidth in a range of about 1 nanosecond to about 50 nanoseconds so as to enhance crystallinity of said doped surface layer while maintaining high above-bandgap, and in many embodiments sub-bandgap optical absorptance.

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm.sup.3 of one another. Other embodiments, including methods, are disclosed.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Provided is a thin film transistor including a highly-textured dielectric layer, an active layer, a gate electrode and a source/drain electrode that are stacked on a base substrate. The source/drain electrode includes a source electrode and a drain electrode. The gate electrode and the active layer are insulated from each other. The source electrode and the drain electrode are electrically connected to the active layer. Constituent particles of the active layer are of monocrystalline silicon-like structures. According to the present disclosure, the highly-textured dielectric layer is adopted to replace an original buffer layer to induce the active layer to grow into a monocrystalline silicon-like structure, such that the performance of the thin film transistor is improved.

Methods and systems for crystallizing a thin film provide a laser beam spot that is continually advanced across tire thin film to create a sustained complete or partial molten zone that is translated across the thin film, and crystallizes to form uniform, small-grained crystalline structures or grains.