A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One potential action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another potential action includes forming additional subsurface laser damage at the first depth position. The substrate surface is illuminated with a diffuse light source arranged perpendicular to a primary substrate flat and positioned to a first side of the substrate, and imaged with an imaging device positioned to an opposing second side of the substrate.

A laser irradiation apparatus including: a laser light source configured to emit a linearly polarized pulsed laser light; a first half-wave plate rotatably provided in an optical path of the pulsed laser light; a first polarization beam splitter configured to branch the pulsed laser light from the first half-wave plate into a first pulsed light and a second pulsed light; a second polarization beam splitter configured to combined the first pulsed light with the second pulsed light, the second pulsed light, the second pulsed light being delayed from the first pulsed light by using an optical path length difference between the first pulsed light and the second pulsed light; and a first wave plate rotatably provided in an optical path of a combined pulsed light generated by combining the first pulsed light with the second pulsed light at the second polarization beam splitter.

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm.sup.3 of one another. Other embodiments, including methods, are disclosed.

A laser annealing apparatus according to an embodiment includes a laser light source, an annealing optical system, a linear irradiation region along a Y-direction, a moving mechanism configured to change a relative position of the irradiation region with respect to the substrate along an X-direction, an illumination light source configured to generate illumination light for illuminating the substrate along a third direction, and a detector configured to detect detection light reflected, in a fourth direction, on the substrate illuminated by the illumination light so as to photograph an annealed part of the substrate in a linear field of view along the Y-direction. In a YZ-plane view, the third direction is inclined from the vertical direction and the fourth direction is inclined from the vertical direction.

A method for manufacturing a semiconductor crystalline thin film according to a viewpoint of the present disclosure includes radiating first pulsed laser light having a first pulse duration to an amorphous semiconductor to poly-crystallize the amorphous semiconductor and radiating second pulsed laser light having a second pulse duration shorter than the first pulse duration to an area of a semiconductor crystal having undergone the poly-crystallization to lower the height of ridges of the semiconductor crystal.

Method for manufacturing an electronic device, comprising the steps of: forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

Process for manufacturing a 3C-SiC layer, comprising the steps of: providing a wafer of 4H-SiC, provided with a surface; heating, through a LASER beam, a selective portion of the wafer at least up to a melting temperature of the material of the selective portion; allowing the cooling and crystallization of the melted selective portion, thus forming the 3C-SiC layer, a Silicon layer on the 3C-SiC layer and a carbon-rich layer above the Silicon layer; completely removing the carbon-rich layer and the Silicon layer, exposing the 3C-SiC layer. If the Silicon layer is maintained on the 4H-SiC wafer, the process leads to the formation of a Silicon layer on the 4H-SiC wafer. The 3C-SiC or Silicon layer thus formed may be used for the integration, even only partial, of electrical or electronic components.

A laser irradiation method includes a first scanning wherein a laser beam is scanned in a first region having a width in the X direction and a length in the Y direction by moving a laser irradiation area on the surface of the substrate along the Y direction using a spot laser beam, and a second scanning wherein laser beam is scanned in a second region having a width in the X direction and a length in the Y direction by moving a laser irradiation area on the surface of the substrate along the Y direction using the spot laser beam. A center of the second region is spaced apart from a center of the first region in the X direction.

Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One potential action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another potential action includes forming additional subsurface laser damage at the first depth position. The substrate surface is illuminated with a diffuse light source arranged perpendicular to a primary substrate flat and positioned to a first side of the substrate, and imaged with an imaging device positioned to an opposing second side of the substrate.