A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.

A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.

A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion of a first semiconductor material and a second portion of a second semiconductor material disposed over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes a semiconductor oxide feature disposed on sidewalls of the first portion and a gate stack disposed on the fin feature. The gate stack includes an interfacial layer over a top surface and sidewalls of the second portion and a gate dielectric layer over the interfacial layer and sidewalls of the semiconductor oxide feature. A portion of the gate dielectric layer is below the interfacial layer.

Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.

A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.

The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

A resistive element in an artificial neural network, the resistive element includes a Silicon-on-insulator (SOI) substrate, and a Silicon layer formed on the Silicon-on-insulator substrate. The Silicon layer includes dopants derived from a thin film dopant layer, and the thin film dopant layer includes a programmed amount of dopant including at least one of Boron and Phosphorus.

A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.