A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.0×10.sup.11 cm.sup.−3.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N.sup.+ region and a P.sup.+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO.sub.2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

Polysilicon films (P1,P2) are simultaneously formed on a wafer (W1) and a monitor wafer (W2) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P2) formed on the monitor wafer (W2) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P1) formed on the wafer (W1) is etched using the selected mask pattern to form the polysilicon resistor (5).

The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same. The may method include: providing a substrate structure that comprises: a substrate comprising encryption device areas and reference device areas; at least one first gate structure on the encryption device areas and used in an encryption device and a first spacer layer on a side wall of the first gate structure; a first interconnection layer on the encryption device areas and the first spacer layer; at least one second gate structure on the reference device areas and used in a reference device and a second spacer layer on a side wall of the second gate structure; and a second interconnection layer on the reference device area and the second spacer layer; performing first ion injection, so as to introduce first impurities into the first interconnection layer; performing second ion injection, so as to introduce second impurities into the first and second interconnection layers, where a password of the device having a physically unclonable function is determined according to a drain current of each encryption device and a drain current of a reference device corresponding to the encryption device.

Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.

A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.

A method of making a semiconductor device includes depositing a first polysilicon layer over a substrate. The method further includes forming a barrier layer over the first polysilicon layer. The method further includes patterning the first polysilicon layer. The method further includes depositing a second polysilicon layer over the barrier layer, wherein the depositing of the second polysilicon layer includes increasing a grain size of the first polysilicon layer, and causing at least one grain boundary in the first polysilicon layer to contact the barrier layer.

A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.