H01L21/2807

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CARBON NANOTUBE GATE
20190385854 · 2019-12-19 ·

A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
20190371904 · 2019-12-05 ·

A thin film transistor and manufacturing methods thereof, an array substrate and a display device are provided. The thin film transistor includes a base substrate, a gate layer, a gate insulating layer, an active layer, and a source/drain layer. The gate layer includes a first gate layer, and a second gate layer between the first gate layer and the gate insulating layer. The first gate layer is a metal layer. The second gate layer is a doped semiconductor material layer. The gate insulating layer is usually made from SiO, SiN or the like.

Semiconductor device with self-aligned carbon nanotube gate

A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

POLYSILICON GATE FORMATION IN CMOS TRANSISTORS
20190206689 · 2019-07-04 ·

A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.

Method of forming silicon hardmask

A method for manufacturing a semiconductor device includes patterning a plurality of fins on a semiconductor substrate, wherein a hardmask is formed on each of the plurality of fins, forming a dielectric layer on the semiconductor substrate between the plurality of fins, removing the hardmasks from each of the plurality of fins, forming a plurality of cap layers in place of the removed hardmasks on each of the plurality of fins, wherein the plurality of cap layers comprise at least one of amorphous silicon and polycrystalline silicon, and selectively recessing the dielectric layer with respect to the plurality of cap layers.

Method for manufacturing display panel, and display device

A method for manufacturing a display panel, and a display device are disclosed. The method for manufacturing a display panel includes: providing a TFT substrate; dispersing graphene and metal nanowires in a hydrophilic solvent to form a hydrophilic conductive ink; applying the hydrophilic conductive ink onto the TFT substrate to form a composite electrode layer; forming, on the composite electrode layer, a pixel defining layer having a plurality of openings at least partially exposing the composite electrode layer; applying hydrophilic organic ink into the plurality of openings of the pixel defining layer to form an organic layer; drying the composite electrode layer and the organic layer to form a first electrode and an organic light emitting structure; and forming a second electrode on the organic light emitting structure and the pixel defining layer.

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CARBON NANOTUBE GATE
20180350603 · 2018-12-06 ·

A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

METHOD FOR MANUFACTURING DISPLAY PANEL, AND DISPLAY DEVICE
20180308914 · 2018-10-25 ·

A method for manufacturing a display panel, and a display device are disclosed. The method for manufacturing a display panel includes: providing a TFT substrate; dispersing graphene and metal nanowires in a hydrophilic solvent to form a hydrophilic conductive ink; applying the hydrophilic conductive ink onto the TFT substrate to form a composite electrode layer; forming, on the composite electrode layer, a pixel defining layer having a plurality of openings at least partially exposing the composite electrode layer; applying hydrophilic organic ink into the plurality of openings of the pixel defining layer to form an organic layer; drying the composite electrode layer and the organic layer to form a first electrode and an organic light emitting structure; and forming a second electrode on the organic light emitting structure and the pixel defining layer.

Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures

Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70? C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

SEMICONDUCTOR DEVICE WITH CAPPING LAYER
20240304696 · 2024-09-12 ·

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.