The present application discloses a method for manufacturing a high-voltage metal gate device. After the deposition of a gate metal through a normal process, in CMP processes performed to the gate metal, firstly a first CMP process is performed to thin the gate metal to a certain thickness in advance, then a blocking dielectric layer is deposited, a large-area high-voltage gate region is opened through photolithography, and the blocking dielectric layer other than the blocking dielectric layer in the large-area high-voltage gate region is removed through etching. In a second CMP process performed to the gate metal, due to the blocking dielectric layer on the surface of the large-area gate metal in the high-voltage gate region, the polishing speed is slow, and CMP dishing will not be caused.

A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

A removal composition and process for selectively removing a first metal gate material (e.g., titanium nitride) relative to a second metal gate material (e.g., tantalum nitride) from a microelectronic device having said material thereon. The removal composition can include fluoride or alternatively be substantially devoid of fluoride. The substrate preferably comprises a high-k/metal gate integration scheme.

Method of forming film stacks and film stacks for electronic devices are described herein. The methods comprise depositing a molybdenum nucleation layer on a gate oxide layer; depositing a molybdenum layer on the molybdenum nucleation layer; and performing a plasma nitridation process to insert nitrogen atoms into the molybdenum layer to form a work function modulating layer having an effective work function ≤ 4.5 eV. The plasma nitridation process comprises exposing the molybdenum layer to a radical-rich plasma comprising one or more of N.sub.2 or NH.sub.3. Some methods further comprise one or more of annealing the work function modulating layer, depositing a conductive layer on the work function modulating layer, or performing an etch process.

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H.sub.3PO.sub.4 solution.

A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

There is provided a semiconductor device including a channel portion, and a gate electrode provided on a side opposite to the channel portion with a gate insulating film interposed between the gate electrode and the channel portion, in which the gate insulating film incudes a first portion having a first transition metal oxide, and a second portion having a second transition metal oxide and cation species and having a concentration of the cation species different from the first portion.

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.