In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

A semiconductor component includes a semiconductor substrate, a first oxide layer, an oxide, a first polysilicon layer, a first metal layer, a first mask on the first metal layer, and a bitline. The semiconductor substrate includes an array region, a periphery region and a boundary open region. The boundary open region isolates the array region from the periphery region. The first oxide layer is deposited on the array region. The first polysilicon layer is deposited on the periphery region. The first metal layer is deposited on the first polysilicon layer. A trench is formed on the array region and passes through the first oxide layer. The bitline includes a second polysilicon layer filling in the trench and a second metal layer on the second polysilicon layer. A second mask is formed on the second metal layer. The second polysilicon layer is flush with the first oxide layer.

A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.

A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.