The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.

The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.

A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 10.sup.19 cm.sup.−3 and about 10.sup.20 cm.sup.−3.

Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.

The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.