A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.

Embodiments described herein may be related to apparatuses, processes, and techniques related to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector between the adjacent gates that electrically couples the first fin and the second fin. Other embodiments may be described and/or claimed.

A semiconductor structure includes a first gate stack across a first semiconductor fin structure, a second gate stack across a second semiconductor fin structure, a dielectric fin structure between the first semiconductor fin structure and the second semiconductor fin structure, and a gate cut isolation structure over the dielectric fin structure and between the first gate stack and the second gate stack. The gate cut isolation structure includes a protection layer and a fill layer over the protection layer, and the protection layer and the fill layer are made of different materials.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

The semiconductor device includes an Si chip which has a main surface facing a {100} plane, a trench which is formed by digging down the main surface and has an open end extending inclined in a <110> direction side with respect to a <100> direction in a plan view, and an oxide film which is constituted of an oxide of the Si chip and formed as a film on the main surface and at the open end.