A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.

A method includes providing a semiconductor structure including a device fin protruding from a substrate, forming a dummy gate stack over the device fin, forming a first spacer over the device fin and the dummy gate stack, forming a second spacer over the first spacer, forming a dielectric feature adjacent to the second spacer, and replacing the dummy gate stack with a metal gate stack. Thereafter, the method removes the second spacer, thereby forming an air gap between the first spacer and the dielectric feature and wrapping around the device fin. The method then forms a sealing layer over the first spacer and the dielectric feature, thereby sealing the air gap.

Methods and devices that provide for a fin structure and a dielectric fin structure. A gate structure is formed over the fin structure and the hybrid fin structure. A plurality of dielectric layers is adjacent the gate structure and over the hybrid fin structure between the gate structure and a contact element over the dielectric fin structure. The plurality of dielectric layers includes an air gap, formed by removal of a dummy spacer layer.

The present application provides a metal gate structure of a high-voltage device and a method for making the same, forming a dummy gate on the gate oxide layer, wherein the dummy gate is composed of a plurality of polysilicon structures spaced apart from each other; forming a protective layer on sidewalls of the plurality of polysilicon structures and on the gate oxide layer between the polysilicon structures; performing covering with an insulating layer to fill a region between the polysilicon structures, wherein the filled region forms an insulating structure; removing the polysilicon structure to form a groove; forming a metal layer, wherein the metal layer covers the insulating structure and fills the groove; and polishing the surface of the metal layer, wherein the insulating structure, the protective layer, and the metal layer form a metal gate with a planarized surface.

A semiconductor arrangement is provided and includes a gate electrode. The gate electrode includes a first portion over a first interface between an active region and an isolation structure and a second portion over the active region. The first portion has a first material composition. The second portion has a second material composition different than the first material composition.

The present application provides a method for preparing a semiconductor device with an air gate spacer for reducing parasitic capacitance. The method includes forming a stacking structure on a semiconductor substrate; forming a first sidewall spacer, a second sidewall spacer and a sacrificial sidewall spacer on a sidewall of the stacking structure; and removing the sacrificial sidewall spacer to form an air gap between the first and second sidewall spacers. The sacrificial sidewall spacer is located between the first and second sidewall spacers, and the first and second sidewall spacers have an etching selectivity with respect to the sacrificial sidewall spacer.

A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.

A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.