A pressure sensor die especially suitable for high-temperature, high-pressure operating environment and delivering accurate and reliable pressure measurement at low cost. A single crystalline silicon includes a cap, a substrate and a base connected together. A recess formed on the cap creates an upper sealed cavity with the substrate. A silicon oxide layer is formed between the substrate and the cap. A recess formed on the base creates a lower sealed cavity with the substrate. The upper sealed cavity and the lower sealed cavity overlap in their projections. The substrate includes at least two sets of piezoresistive sensing elements located within the overlapping projections, perpendicular to each other, and oriented in different crystallographic directions.

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes an isolation feature over the substrate and over sides of the fin feature; a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.

The present invention inter alia relates to a supported silica bilayer (SiO.sub.2 bilayer) film. In the supported silica bilayer film, the silica bilayer film consists of two atomic layers of corner-sharing SiO.sub.4 tetrahedra, forms in itself a chemically saturated structure and contains pores. The silica bilayer film has a first (1) and a second side (2) and is supported on the first side (1) by a removable polymer film. The invention further relates to a process for producing the supported silica bilayer film, a process for transferring a silica bilayer film, a free-standing silica bilayer film, a stack comprising a plurality of silica bilayer films, a filed-effect transistor having a gate oxide comprising the silica bilayer film or a stack thereof and the use of a silica bilayer film.

A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 11014 atoms/cm3 and/or germanium at a concentration of at least about 11019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

A semiconductor device, an electronic apparatus, and a method of manufacturing a semiconductor device with reduced RTN influence regardless of gate electrode shape are disclosed. In one example, a semiconductor device includes a substrate having an element region and an element separating region, the element region including a source region and a drain region, and a channel region between the source and drain regions. The element separating region is arranged on both sides in a direction orthogonal to the source, channel and drain region arrangement direction. A gate insulating film is provided on the element region of the substrate from one side to another side of the element separating region. A gate electrode is provided on the gate insulating film, and includes an impurity having a different concentration in a boundary region as compared to a central region.

A semiconductor device includes a SOI substrate, first and second active elements, and an interconnect structure. The SOI substrate includes a semiconductor layer which includes first and second semiconductor blocks separated from each other by an isolation structure. The first and second active elements are disposed on the first and second semiconductor blocks respectively. A source/drain region of the first active element is electrically connected to a gate structure of the second active element through a first path provided by the interconnect structure. The second semiconductor block is electrically connected to the second semiconductor block through a second path provided by the interconnect structure. The second path includes a contact that is in contact with the upper surface of the second semiconductor block.

A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.

A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.

Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer.