A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

A method of fabricating a semiconductor structure includes forming a plurality of Fin structures, doping first dopants at both sides of a first Fin structure of the Fin structures, and providing a first thermal diffusion operation to the semiconductor structure. The method also includes doping second dopants at both sides of a second Fin structure of the Fin structures, and providing a second thermal diffusion operation to the semiconductor structure. A first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and a second gate length for the second Fin structure using the second thermal diffusion operation. The first dopants are of the same type or a different type.

Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.

Embodiments described herein relate to a method of manufacture of an LDMOS transistor an LDMOS transistor, and an integrated circuit comprising an LDMOS transistor. The method of manufacture of the LDMOS device comprises implanting a Fluorine dopant in a drift region of the LDMOS device in order to improve alignment between the drift region of the LDMOS transistor and a thicker area of a single gate oxide layer grown on the drift region and a channel region of the LDMOS transistor.

Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

Semiconductor devices include vertically stacked channel layers formed from a semiconductor material. A metallic interface layer is formed between metal source/drain regions and the vertically stacked channel layers. The metallic interface layer includes the semiconductor material and a metal. A gate stack is formed between and around the channel layers.

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.