A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

A method of forming an oxide structure is disclosed. The method includes forming trenches on a top surface of a substrate and performing a surface treatment process on the substrate. The surface treatment includes forming an amorphous layer on the substrate, removing a portion of the amorphous layer to form a liner layer, and forming a dielectric liner on the liner layer. The liner layer formed are substantially uniform in thickness to prevent contamination and pinhole defects on the oxide structure.

The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.

A method of forming an oxide structure is disclosed. The method includes forming trenches on a top surface of a substrate and performing a surface treatment process on the substrate. The surface treatment includes forming an amorphous layer on the substrate, removing a portion of the amorphous layer to form a liner layer, and forming a dielectric liner on the liner layer. The liner layer formed are substantially uniform in thickness to prevent contamination and pinhole defects on the oxide structure.

The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

By depositing a layer of metal on the semiconductor surface where the metal is deposited in a non-oxidized state first and then depositing a layer of the high-k oxide material over the layer of metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.