A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.

An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. A metal-doped insulator layer is in contact with sidewalls of the channel layers. The metal-doped insulator layer is annealed to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers. The metal-doped insulator layer is etched back to form inner spacers. Source/drain regions are formed in contact with the metallic layer. The sacrificial layers are etched away and a gate stack is formed on and around the channel layers.

The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.

Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.

A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.

A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.

Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.

A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.