A substrate processing method includes: a carry-in step of carrying a substrate having a silicon-containing film on a surface of the substrate into a processing container; a first step of forming an adsorption layer by supplying an oxygen-containing gas into the processing container and causing the oxygen-containing gas to be adsorbed on a surface of the silicon-containing film; a second step of forming a silicon oxide layer by supplying an argon-containing gas into the processing container and causing the adsorption layer and the surface of the silicon-containing film to react with each other with plasma of the argon-containing gas; and a third step of forming a graphene film on the silicon oxide layer by supplying a carbon-containing gas into the processing container with plasma of the carbon-containing gas.

In some aspects, the techniques described herein relate to a semiconductor device including: a substrate having a first side and a second side, the second side being opposite the first side; active circuitry disposed on the first side of the substrate; a metallic implant disposed in the substrate, the metallic implant being a blanket implant on the second side of the substrate; and a metallic layer disposed on the second side of the substrate, the metallic layer and the second side of the substrate including the metallic implant defining an ohmic contact.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

Techniques for reducing the specific contact resistance of metal - semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal - group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process is performed on a metal nitride layer in a film stack, thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments eliminating an oxygen-containing interfacial layer disposed within the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift. Further, the metal gate structure operates with an increased leakage current that is as little as one quarter the increase in leakage current associated with a similar metal gate structure formed via conventional techniques.

The embodiment relates to a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. According to the embodiment, a light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first electrode electrically connected with the first conductive semiconductor layer, a second electrode electrically connected with the second conductive semiconductor layer, an insulating member provided on the light emitting structure while exposing the first electrode and the second electrode, a third electrode provided on the first electrode, and a fourth electrode provided on the second electrode. The third electrode includes a first part of the third electrode directly making contact with the first electrode and a second part of the third electrode, which is provided on the first part of the third electrode and has a horizontal width wider than the first part of the third electrode, and the fourth electrode includes a first part of the fourth electrode directly making contact with the second electrode and a second part of the fourth electrode, which is provided on the first part of the fourth electrode and has a horizontal width wider than the first part of the fourth electrode. The light extraction efficiency and the heat radiation characteristic may be improved, and the reliability may be improved.

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Disclosed is a method for removing, from a target substrate having an insulating film with a predetermined pattern formed thereon, a silicon-containing oxide film formed in a silicon portion at a bottom of the pattern. The method includes: forming a carbon-based protective film on the entire surface of the insulating film including the pattern by ALD using a carbon source gas; selectively removing the carbon-based protective film on an upper surface of the insulating film and on the bottom of the pattern by an anisotropic plasma processing; removing the silicon-containing oxide film formed on the bottom of the pattern by etching; and removing a remaining portion of the carbon-based protective film.