Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a fin protruding from a substrate and a gate stack formed across the fin. The semiconductor structure further includes a source/drain structure attaching to the gate stack and a contact structure connecting to the source/drain structure. The semiconductor structure further includes a first cap layer covering a top surface of the contact structure. In addition, the first cap layer includes a first halogen

Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm.sup.−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a fin protruding from a substrate and a gate stack formed across the fin. The semiconductor structure further includes a first cap layer formed over the gate stack and a source/drain structure formed adjacent to the gate stack in the fin. The semiconductor structure further includes a contact structure formed over the source/drain structure and a second cap layer formed over the contact structure. In addition, the first cap layer and the second cap layer include different halogens.

The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.

A semiconductor structure is provided. The semiconductor structure includes a base substrate; and a first doped epitaxial layer and a second doped epitaxial layer in the base substrate. Each of the first and second doped epitaxial layers is corresponding to a different gate structure on the base substrate. The semiconductor structure further includes a repaired dielectric layer formed on and surrounding each of the first and second doped epitaxial layer; a metal layer on the repaired dielectric layer; an interlayer dielectric layer over the base substrate and covering tops of gate structures; and a conductive plug on the metal layer and through the interlayer dielectric layer.

Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.