The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

A display device includes: a substrate including first and second light-blocking areas, and a pixel area; a light-blocking pattern at least partially at the first light-blocking area; a data line at the second light-blocking area; a first insulating layer on the light-blocking pattern and the data line; a semiconductor layer on the first insulating layer and overlapping the light-blocking pattern on a plane; a second insulating layer on the semiconductor layer; a color filter on the second insulating layer at least partially at the pixel area; a third insulating layer on the second insulating layer and the color filter; a gate line on the third insulating layer at the first light-blocking area; a pixel electrode at least partially at the pixel area; and a bridge electrode at least partially at the first light-blocking area. The second and third insulating layers directly contact one another over the semiconductor layer.

A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.

A method for manufacturing a field effect transistor including a gate-insulating layer, an active layer, and a passivation layer. The method includes a first process of forming the gate-insulating layer; and a second process of forming the passivation layer. At least one of the first process and the second process includes: forming a first oxide containing an alkaline earth metal and at least one of gallium, scandium, yttrium, and a lanthanoid; and etching the first oxide by use of a first solution containing at least one of hydrochloric, acid, oxalic acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, and hydrogen peroxide water.

A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn).

A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices.

Methods and apparatus for processing a substrate are provided herein. For example, a method can include depositing a first metal layer on a substrate and etching the first metal layer to form a gate electrode, depositing a dielectric layer atop the gate electrode, depositing a semi-conductive oxide layer atop the dielectric layer to cover a portion of the gate electrode, etching the dielectric layer from a portion of the gate electrode that is not covered by the semi-conductive oxide layer to form a gate access via, and depositing a second metal layer atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.