A semiconductor device having high reliability is provided.

A first conductor is formed, a first insulator is formed over the first conductor, a second insulator is formed over the first insulator, a third insulator is formed over the second insulator, microwave-excited plasma treatment is performed on the third insulator, an island-shaped first oxide semiconductor is formed over the third insulator and a second conductor and a third conductor are formed over the first oxide semiconductor, an oxide semiconductor film is formed over the first oxide semiconductor, the second conductor, and the third conductor, a first insulating film is formed over the oxide semiconductor film, a conductive film is formed over the first insulating film, a fourth insulator and a fourth conductor are formed by partly removing the first insulating film and the conductive film, a second insulating film is formed to cover the oxide semiconductor film, the fourth insulator, and the fourth conductor, a second oxide semiconductor and a fifth insulator are formed by partly removing the oxide semiconductor film and the second insulating film to expose a side surface of the first oxide semiconductor, a sixth insulator is formed in contact with the side surface of the first oxide semiconductor and a side surface of the second oxide semiconductor, a seventh insulator is formed in contact with the sixth insulator, and heat treatment is performed.

To provide a semiconductor device with favorable electrical characteristics. To provide a method for manufacturing a semiconductor device with high productivity. To reduce the temperatures in a manufacturing process of a semiconductor device. An island-like oxide semiconductor layer is formed over a first insulating film; a second insulating film and a first conductive film are formed in this order, covering the oxide semiconductor layer; oxygen is supplied to the second insulating film through the first conductive film; a metal oxide film is formed over the second insulating film in an atmosphere containing oxygen; a first gate electrode is formed by processing the metal oxide film; a third insulating film is formed, covering the first gate electrode and the second insulating film; and first heat treatment is performed. The second insulating film and the third insulating film each include oxide. The highest temperature in the above steps is 340 C. or lower.

A thin film transistor includes a gate electrode. The thin film transistor further includes an oxide semiconductor layer which includes at least indium and is usable as a channel layer, wherein a region of the oxide semiconductor layer closest to the gate electrode includes fluorine. The thin film transistor further includes a gate insulating layer between the gate electrode and the oxide semiconductor layer. The thin film transistor further includes a fluorine-including layer which includes fluorine and is between the gate electrode and the gate insulating layer.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.

What is proposed is a method of producing at least two differently heavily doped subzones (3, 5) predominantly doped with a first dopant type in a silicon substrate (1), in particular for a solar cell. The method comprises: covering at least a first subzone (3) of the silicon substrate (1) in which a heavier doping with the first dopant type is to be produced with a doping layer (7) of borosilicate glass, wherein at least a second subzone (5) of the silicon substrate (1) in which a lighter doping with the first dopant type is to be produced is not covered with the doping layer (7), and wherein boron as a dopant of a second dopant type differing from the first dopant type and oppositely polarized with respect to the same is included in the layer (7), and; heating the such prepared silicon substrate (1) to temperatures above 300 C., preferably above 900 C., in a furnace in an atmosphere containing significant quantities of the first dopant type. Additionally, at least a third doped subzone (15) doped with the second dopant type may be produced by the method additionally comprising, prior to the heating, a covering of the doping layer (7), above the third doped subzone (15) to be produced, with a further layer (17) acting as a diffusion barrier for the first dopant type.

The method uses the observation that a borosilicate glass layer seems to promote an in-diffusion of phosphorus from a gas atmosphere and may substantially facilitate a manufacturing for example of solar cells, in particular back contact solar cells.

An oxide semiconductor device includes a first insulation layer pattern and a second insulation layer pattern disposed on a substrate, an active layer disposed on the first and second insulation layer patterns, the active layer including a source region including the first insulation layer pattern, a drain region including the second insulation layer pattern, and a channel region disposed between the source and drain regions, a source electrode contacting the source region, and a drain electrode contacting the drain region.

A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate trench located in the substrate; a gate oxide layer located on a side wall and a bottom of the gate trench; and a gate conductive layer located on a surface of the gate oxide layer, a top of the gate conductive layer being lower than a top of the gate trench. The gate oxide layer includes an ion implantation area. A bottom of the ion implantation area is higher than a bottom of the gate conductive layer and lower than the top of the gate conductive layer, and a top of the ion implantation area is higher than or flush with the top of the gate conductive layer.

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.