Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/02
Manufacture or treatment of semiconductor devices or of parts thereof
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H01L21/04
the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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H01L21/50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07; e.g. sealing of a cap to a base of a container
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H01L21/60
Attaching; or detaching; leads or other conductive members, to be used for carrying current to or from the device in operation
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H01L2021/60007
involving a soldering or an alloying process
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H01L2021/60022
using bump connectors, e.g. for flip chip mounting
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H01L2021/60225
Arrangement of bump connectors prior to mounting
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H01L2021/6024
wherein the bump connectors are disposed only on the mounting substrate
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H01L2021/6024

NOVEL THREE DIMENSIONAL INTEGRATED CIRCUITS STACKING APPROACH
20170040290 · 2017-02-09 ·

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.