There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Memory devices might include an array of memory cells and a control logic to control access of the array of memory cells, where a memory cell of the array of memory cells might include a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, wherein the charge storage structure comprises a charge-storage material and a gettering agent.

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

The present disclosure relates to a flash memory having a plurality of control gates, including: a substrate. An oxide layer disposed on the substrate. A fin-shaped channel layer disposed on the oxide layer, and includes a first end portion, a second end portion, a top surface and two side surfaces, wherein the top surface and the two side surfaces are located between the first end portion and the second end portion, the top surface faces away from the oxide layer and separates the two sides. The two charge storage structures are respectively disposed on the two sides of the fin channel layer. The two gates are disposed on the oxide layer and respectively contact with the two charge storage structures. Two word conductive pillars are connected to the two gates respectively and extending from the two gates in a direction leaving the oxide layer.

The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

A storage device includes a crystalline silicon substrate, a stacked film including a plurality of crystalline silicon films provided on the crystalline silicon substrate and extending parallel to a crystalline silicon substrate surface and a plurality of insulating films extending parallel to the crystalline silicon substrate surface between the respective crystalline silicon films, a plurality of first conductive layers each having a disconnected end portion penetrating at least a portion of the stacked film and located below the stacked film, memory cells provided respectively between the plurality of crystalline silicon films and the plurality of first conductive layers, and a plurality of second conductive layers electrically connected to the plurality of crystalline silicon films respectively.

A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.