The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.

A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

A transistor device includes field plate contacts that electrically connect overlying contact pads to field electrodes in underlying trenches, and mesa contacts that electrically connect the contact pads to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

A semiconductor device includes a semiconductor part, first to third electrodes, and first and second control electrodes. The semiconductor part is provided between the first and second electrodes. On the second electrode side of the semiconductor part, the first control electrode and the third electrode are provided in a first trench, and the second control electrode is provided in a second trench. The first control electrode is provided between the second and third electrode. In a first direction from the first control electrode toward the second control electrode, the first trench has first and second widths. The first width is a combined width of the third electrode and insulating portions provided on both sides of the third electrode. The second width is a combined width of the first control electrode and the gate insulating films on both sides thereof. The first width is greater than the second width.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.

A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.