A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

A method of manufacturing a split-gate type nonvolatile memory improving reliability and manufacturing yield. In a method of manufacturing a split-gate type nonvolatile memory in which a memory gate electrode is formed prior to a control gate electrode, a protective film is formed to cover the gate insulating film exposed between control gate electrodes before unnecessary control gate electrodes are removed.

A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a first insulating layer, a source and a drain, a stacked structure, a second insulating layer, and a gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed on the first insulating layer, and the stacked structure is also disposed on the first insulating layer, between the source and the drain. The stacked structure includes a charge storage layer and an oxide semiconductor (OS) layer disposed on the charge storage layer. The second insulating layer covers the source, the drain and the OS layer. The gate is disposed on the second insulating layer.

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.