A method for forming a 3D memory device is disclosed. A gate electrode having an inverted “T” shape is formed above a substrate. A continuous blocking layer is formed on the gate electrode. A continuous charge trapping layer is formed on the blocking layer. A first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically. The second part of the charge trapping layer extending vertically is removed to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally. A continuous tunneling layer is formed on the discrete charge trapping layers. A continuous channel layer is formed on the tunneling layer.

A charge trapping nonvolatile memory device includes a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each other by a first trapping region, a channel region, and a second trapping region. A gate stack structure is disposed over the channel region. A first stack including a tunnel insulation layer, a first charge trap layer, and a first blocking insulation layer are disposed over the first trapping region. A second stack including a tunnel insulation layer, a second charge trap layer, and a second blocking insulation layer are disposed over the second trapping region. An interlayer insulation layer is disposed over the substrate and covers the gate stack structure. A first contact plug and a second contact plug penetrate the interlayer insulation layer and respectively contact the source region and the drain region. A third contact plug penetrates the interlayer insulation layer, contacts the gate stack structure, and overlaps with the first and the second charge trap layers.

Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

A semiconductor device is provided. The semiconductor device includes an electrode structure that has gate electrodes that are sequentially stacked on a semiconductor layer, vertical structures that penetrate the electrode structure, and horizontal structures that extend in a third direction below the electrode structure. The vertical structures extend in a first direction and are spaced apart from each other in a second direction that crosses the first direction. Each of the vertical structures includes vertical channel patterns arranged in the first direction. The horizontal structure includes horizontal channel patterns. Each of the horizontal channel patterns is connected to at least three of the vertical channel patterns.

The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.

A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

A cheap and high performance 1.5 transistor-type flash memory highly compatible to external of memory region is provided. The flash memory has sacrifice film formed on substrate. U-shaped groove is formed on sacrifice film, where multiple insulating film is laminated. Multiple insulating film includes silicon nitride film as charge storage layer. Low resistive material is disposed on multiple insulating film to form control gate. Select gate is formed on insulating film on side of control gate in self-aligned manner. Semiconductor regions opposite in conductivity to substrate on both sides of adjoining control gate and select gate to form source and drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with adjoining control gate and select gate between source and drain. In MOS-type transistor with control gate, threshold voltage is changeable according to injection/emission of charge to silicon nitride as charge storage layer, and thus work as non-volatile memory.

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.