A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

A vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulation pattern is disposed on a portion of an outer sidewall of the channel that is adjacent to each of the gate electrodes. Charge trapping pattern structures are disposed between the tunnel insulation pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes upper and lower charge trapping patterns spaced apart from each other in the vertical direction. Blocking pattern structures are between the charge trapping patterns and each of the gate electrodes. A first portion of the channel that is adjacent to the tunnel insulation pattern has a thickness in a horizontal direction that is smaller than a thickness of other portions of the channel.

A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A NAND memory string extending vertically through a dielectric stack including a plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A slit opening extending vertically through the interleaved sacrificial layers and dielectric layers of the dielectric stack is formed. A plurality of lateral recesses is formed by removing the sacrificial layers through the slit opening. A plurality of gate-to-gate dielectric layers are formed by oxidizing the dielectric layers through the slit opening and the lateral recesses. A memory stack including a plurality of interleaved gate conductive layers and the gate-to-gate dielectric layers by depositing the gate conductive layers into the lateral recesses through the slit opening.

One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.

A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.

Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.