Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.

A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.

A method for manufacturing a semiconductor device includes a step of reducing a thickness of a silicon oxide film embedded in an element isolation trench including fins in order to form protruded fins. In the step, the silicon oxide film is etched while covering part of an upper surface of the silicon oxide film with a resist pattern. At this time, the resist pattern is formed such that a distance between the fin and the resist pattern is equal to or less than a predetermined interval which is an arrangement interval of the plurality of fins.

A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.

A manufacturing method of a semiconductor device includes the following steps. Trenches are formed on a substrate, and the trenches are formed on a first region and a second region defined on the substrate. A barrier layer is formed conformally in the trenches. A first pull-down process is performed to the barrier layer on the second region. The barrier layer on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer on the first region. The barrier layer on the second region is covered by a second mask during the second pull-down process. A proportion of an area of the trenches on the first region to an area of the first region is different from a proportion of an area of the trenches on the second region to an area of the second region.