A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

Embodiments relate to the field of semiconductor technology, and propose a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a channel layer including a group III-V semiconductor and a group III-V semiconductor layer, the group III-V semiconductor and the group III-V semiconductor layer forming a heterojunction; a gate structure positioned on the channel layer, the gate structure including a gallium oxide layer, a gate oxide layer, and a gate electrode stacked in sequence; a source electrode positioned at an end of the heterojunction; and a drain electrode positioned at other end of the heterojunction.

Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

A semiconductor structure includes a substrate with a plurality of word line trenches and source/drain regions each adjacent to each word line trench; a word line located in the word line trench, which includes a first conductive layer located at a bottom of the word line trench, a single junction layer and a second conductive layer stacked in sequence, in which a projection of the word line on a sidewall of the word line trench and the projection of the source/drain region on the sidewall of the word line trench have an overlapping region with a preset height, and when a voltage applied to the word line is less than a preset voltage, a resistance of the single junction layer is greater than the preset resistance, to make the first conductive layer and the second conductive layer disconnected.

A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

There is provided a semiconductor device including: a semiconductor layer including a main surface; a plurality of trenches including a plurality of first trench portions and a plurality of second trench portions, respectively; an insulating layer formed in an inner wall of each of the second trench portions; a first electrode buried in each of the second trench portions with the insulating layer interposed between the first electrode and each of the second trench portions; a plurality of insulators buried in the first trench portions so as to cover the first electrode; a contact hole formed at a region between the plurality of first trench portions in the semiconductor layer so as to expose the plurality of insulators; and a second electrode buried in the contact hole.

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.

A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.