A semiconductor device includes a body, a gate oxide layer, and a gate electrode. The body is defined by a drift region and one or more implant regions. A junction field effect region is defined between one of the implant regions and another one of the implant regions. The gate oxide layer is grown as a single, unitary structure extending across the semiconductor body and at least partially overlap the implant regions. The gate oxide layer is additionally defined by a central expansion region between the implant regions, and extend into the junction field effect region. A gate electrode is disposed on the gate oxide layer.

In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

An object of the present disclosure is to achieve a stable current sensing operation and suppress decrease in main current at a low temperature of 0° C. or less in a silicon carbide semiconductor device. An SiC-MOSFET includes: a main cell outputting main current; and a sense cell outputting sense current proportional to the main current, wherein temperature dependent properties of the main current differ in accordance with threshold voltage of the main cell, temperature dependent properties of the sense current differ in accordance with threshold voltage of the sense cell, the threshold voltage of the main cell is smaller than the threshold voltage of the sense cell, and in a temperature of 0° C. or less, an inclination of the temperature dependent properties of the main current is smaller than an inclination of the temperature dependent properties of the sense current.

A semiconductor device includes: a chip having a main surface; a first conductive type first region formed on a surface layer portion of the main surface; a second conductive type second region formed on a surface layer portion of the first region; a drain region formed on a surface layer portion of the second region; a source region formed on the surface layer portion of the first region at a distance from the second region; and a second conductive type floating region formed in the first region at a thickness position between a bottom portion of the first region and a bottom portion of the second region and being spaced apart from the bottom portion of the second region, wherein the floating region faces the second region with a portion of the first region interposed between the floating region and the second region.

A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.

A semiconductor device includes: an n.sup.−-type epitaxial layer having an element main surface; a p.sup.−-type body region, an n.sup.+-type source region, and n.sup.+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p.sup.+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.

A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

A bottom of a trench is an Si plane or a C plane while sidewalls of the trench are an m-plane. In the trench, a gate electrode is provided via a gate insulating film. The gate insulating film is a HTO film with a thickness of at least 50 nm. By a post-HTO-deposition annealing at a temperature in a range of 1250 degrees C. to 1300 degrees C. under a mixed gas atmosphere containing nitric oxide, nitrogen, and oxygen, the film density of the gate insulating film is within a range of 2.21 g/cm.sup.3 to 2.38 g/cm.sup.3. The total oxygen flow amount of the mixed gas atmosphere of the post-HTO-deposition annealing is at most 5%. The gate insulating film has a two-layer structure including a low-density film that is within 3 nm from a SiC/SiO.sub.2 interface and has a relatively low film density, and a high- density film that is at least 3 nm apart from the SiC/SiO.sub.2 interface and has a relatively high film density.

A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.