A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

A circular LDMOS device includes a lower drift layer disposed on a substrate, a drain region disposed on the lower drift layer, a source region having a circular ring shape surrounding the drain region and spaced apart from the drain region, a field insulating layer disposed between the drain region and the source region, and an upper drift layer disposed between the lower drift layer and the field insulating layer and having a conductivity type different from that of the lower drift layer.

A semiconductor device including at least one nanosheet and epitaxial source and drain regions are present on opposing ends of the at least one nanosheet. A gate structure is present on a channel of the at least one nanosheet. The gate structure includes a first work function metal gate portion present at a junction portion of the source and drain regions that interfaces with the channel portion of the at least one nanosheet, and a second work function metal gate portion present on a central portion of the channel of the at least one nanosheet. The amount of metal containing nitride in the second work function metal gate portion is greater than an amount of metal containing nitride in the first work function metal gate portion. The device further includes a rotated T-shaped dielectric spacer present between the gate structure and the epitaxial source and drain regions.