The semiconductor device includes a first gate electrode, a first gate insulating film, a semiconductor film, a first electrode, a second electrode, a second gate insulating film, and a second gate electrode. The first gate insulating film is located over the first gate electrode. The semiconductor film is located over the first gate insulating film and overlaps with the first gate electrode. The first electrode and the second electrode are each located over and in contact with the semiconductor film. The second gate insulating film is located over the first electrode and the second electrode. The second gate electrode is located over the second gate insulating film and overlaps with the second electrode and the first gate electrode. The first electrode is completely exposed from the second gate electrode.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

A display substrate and a method of manufacturing a display substrate, the display substrate including a base substrate; a gate electrode on the base substrate; an insulation layer on the gate electrode; a source electrode and a drain electrode on the insulation layer and overlapping the gate electrode; and a pixel electrode electrically connected to the drain electrode, wherein a cavity is formed between the gate electrode and the insulation layer.

A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

A structure of a protruding gate transistor is disclosed. The protruding gate transistor comprising a substrate, a source region, a drain region, a channel extension anchor, a channel layer, and gate structure. The gate structure comprising a gate insulator layer, and a gate conductor layer. The channel layer is formed to be protruding from the substrate to extend the length of the channel of the protruding gate transistor and alleviate from channel length modulation.

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Provided are a thin film transistor structure, a manufacturing method thereof, and a display device. The method comprises: providing a substrate (10), and sequentially forming a gate (20), a gate insulating layer (30), an active layer (40), a doped layer (50), a source (610), a drain (620) and a channel region (70) on the substrate (10); placing the channel region (70) in a preset gas atmosphere for heating treatment; wherein, the channel region (70) is placed in a nitrogen atmosphere to heat for a first preset time, in a mixed atmosphere of nitrogen and ammonia to heat for a second preset time, in an ammonia atmosphere to heat for a third preset time; or first heating the channel region (70) for a fourth preset time, finally placing in the ammonia atmosphere to heat for a fifth preset time.

The present disclosure provides a thin film transistor, a manufacturing method thereof, and a display device, and the thin film transistor of the present disclosure includes: a substrate; a gate, a gate insulating layer, an active layer, a source and drain layer sequentially provided on the substrate, and the source and drain layer is correspondingly provided at a first source contact region and a first drain contact region of the active layer. A planarization layer is provided between the gate insulating layer and the substrate, the planarization layer is in a same layer as the gate and in direct contact with the gate, and an upper surface of the planarization layer is flush with an upper surface of the gate.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.