A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.

A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device under thermal stress and the assembly performance of the semiconductor device in manufacturing steps. The method includes the following: forming a first electrode by depositing a first conductive film onto one main surface of a semiconductor substrate and patterning the first conductive film; forming a first metal film corresponding to a pattern of the first electrode onto the first electrode; forming a second electrode by depositing a second conductive film onto the other main surface of the semiconductor substrate; forming a second metal film thinner than the first metal film onto the second electrode; and collectively forming a third metal film onto each of the first metal film and the second metal film by electroless plating.

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first region of a first conductivity type formed on the first surface side of the semiconductor layer, a second region of a second conductivity type in contact with the first region, a third region of the first conductivity type that is in contact with the second region and exposed from the first surface side of the semiconductor layer, a gate electrode facing the second region through a gate insulating film, a first electrode that is physically separated from the gate electrode and faces the second region and the third region through an insulating film, a second electrode formed on the semiconductor layer and electrically connected to the first region, the second region, and the first electrode, and a third electrode electrically connected to the third region.

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.

An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of doped columns of a second conductivity type. The termination area further comprises a plurality of surface guard ring regions of the second conductivity type dispose near a top surface of the epitaxial layer close to the doped columns of the second conductivity type. In one of the embodiments, one of the surface guard ring regions extending laterally over several of the doped columns in the termination area.

A method for fabricating a semiconductor device includes forming a bit line contact hole in a substrate; forming a first spacer on a sidewall of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material that fills the bit line contact hole over the sacrificial spacer; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to be aligned with the bit line.