A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.

A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad. A method of manufacturing a semiconductor device package is also disclosed.

A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

Even in a case where a pad becomes smaller, solder connection strength is improved. A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.

A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.