The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

A semiconductor structure and a forming method thereof are provided. The method of forming the semiconductor structure includes: providing a wafer having a front surface and a back surface opposite to the front surface; patterning the back surface of the wafer to form a groove extending from the back surface towards the front surface; forming a dielectric layer at a bottom and a side wall of the groove; and forming, on the dielectric layer, a conductive layer filling the groove.

Even in a case where a pad becomes smaller, solder connection strength is improved. A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.

A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.

A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.