A semiconductor device includes a conductor, a semiconductor element, and a bonding layer. The conductor has obverse surfaces and reverse surfaces facing away from each other in a thickness direction. The semiconductor element has a body layer and electrodes projecting toward the obverse surfaces from a side of the body layer that opposes the obverse surfaces in the thickness direction. The bonding layer bonds the obverse surfaces and the electrodes. Each electrode has a base portion in contact with the body layer and a columnar portion projecting from the base portion and in contact with the bonding layer. The electrodes include a first electrode and a second electrode located closer to the periphery of the body layer than is the first electrode as viewed in the thickness direction. The second electrode is larger in area of the columnar portion than the first electrode, as viewed in the thickness direction.

A method and apparatus are described for fabricating a microchip structure (60A) which includes a first chip (41) that is affixed to a lead frame strip (11-18) having a plurality of lead frame pads (11-16) in a circuit mounting area (19) and a planar lead frame inductor coil (17) that is laterally displaced from the circuit mounting area (19), where molded body (61) encapsulates the first chip (41), lead frame pads (11-16) and planar lead frame inductor coil (17).

A module includes a substrate, metal layers and insulating layers laminated on the substrate, a bottom winding made of a metal directly contacting a first metal layer or a second metal layer, a first insulating layer on the bottom winding, a core on the first insulating layer, a second insulating layer on the core, a top winding made of the metal that is located on the core and a portion of the second insulating layer and that directly contacts the first metal layer or the second metal layer, and a third insulating layer on the top winding, electronic components that are located on the third insulating layer, where primary and secondary windings of the transformer are defined by portions of the bottom winding and the top winding and are located on opposite sides of the core from each other.

A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.

Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.

A light emitting device includes at least three light emitting elements arranged side by side, and one or more light transmissive members each containing a phosphor and covering the light emitting elements. The at least three light emitting elements include two outer light emitting elements arranged on outer sides, and an inner light emitting element arranged between the two outer light emitting elements and having a different peak emission wavelength than a peak emission wavelength of the two outer light emitting elements. The phosphor has a longer peak emission wavelength than the peak emission wavelengths of the outer light emitting elements and the peak emission wavelength of the inner light emitting element. The two outer light emitting elements and the inner light emitting element are connected in series.

Provided is a method for producing a joined body, the method including a first step of preparing a laminated body which includes a first member having a metal pillar provided on a surface thereof, a second member having an electrode pad provided on a surface thereof, and a joining material provided between the metal pillar and the electrode pad and containing metal particles and an organic compound, and a second step of heating the laminated body to sinter the joining material at a predetermined sintering temperature, in which the joining material satisfies the condition of the following Formula (I):
(M.sub.1−M.sub.2)/M.sub.1×100≥1.0  (I)
[in Formula (I), M.sub.1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M.sub.2 represents a non-volatile content in the joining material.]

A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.

Provided is an electronic apparatus including an electronic part, a resin member that covers the electronic part, and a plurality of leads each electrically connected to the electronic part, the resin member including a first resin side surface facing one side in a first direction orthogonal to a thickness direction of the resin member, the plurality of leads including a plurality of first side exposed portions arranged along the first resin side surface, each of the plurality of first side exposed portions being exposed from the first resin side surface, each of the plurality of first side exposed portions including a first tapered portion becoming narrower toward the first resin side surface as viewed in the thickness direction, the first tapered portion including a first front surface that faces the same direction as the first resin side surface in the first direction and is flush with the first resin side surface.