A package structure is provided. The package structure includes a circuit substrate and a redistribution layer over the circuit substrate. The package structure includes an interconnect chip disposed between the circuit substrate and the redistribution layer. The package structure includes a plurality of conductive connectors around the interconnect chip. The package structure includes a plurality of dummy bars between the interconnect chip and the conductive connectors. The dummy bars are electrically insulated from the conductive connectors. The package structure also includes an underfill disposed between the circuit substrate and the redistribution layer and encapsulating the interconnect chip, the dummy bars and the conductive connectors.

A semiconductor packaging method adopts a back-side power supply transmission mode, and includes a first interconnection structure and a second interconnection structure on one side of a driver layer, and a third interconnection structure on an opposite side of the driver layer. The driver layer transmits driving signals to a semiconductor device through the first interconnection structure and the second interconnection structure. The driver layer is electrically connected to the third interconnection structure, and the third interconnection structure is used for transmitting a voltage to the driver layer. As a result, the sizes of the interconnection structures are reduced, reducing costs and improving over problems such as voltage drop and delay time. Meanwhile, compared with the layer-by-layer preparation methods, the first interconnection structure and the second interconnection structure can be prepared separately and concurrently before being electrically connected, resulting in shortened packaging time and improved production efficiency.

A logic die for performing a through silicon via (TSV) repair operation and a semiconductor device including the logic die are provided. The semiconductor device includes the logic die including a memory controller and an interface circuit, a plurality of core dies stacked in a vertical direction on the logic die, each of the plurality of core dies including a memory cell array, and a plurality of through silicon vias (TSVs) configured to electrically connect the logic die to the plurality of core dies, the plurality of TSVs including a plurality of operation TSVs and at least one redundancy TSV. The interface circuit includes a plurality of TSV circuit blocks electrically connected to the plurality of TSVs, respectively, and a TSV repair logic configured to perform a repair operation on a first TSV, in which a defect occurs and a first TSV circuit block, electrically connected to the first TSV.

A package structure, a semiconductor structure, and an electronic device are disclosed. The package structure includes: a base; a first pin array, disposed on the base, where the first pin array includes a plurality of first data pins; and a second pin array, disposed on the base, where the second pin array includes a plurality of second data pins. A blank region is disposed between the first pin array and the second pin array, the blank region extends from a center of the base to an edge of the base, an end part of the blank region is outside the first pin array, at least one of the first data pins and/or at least one of the second data pins are/is adjacent to the blank region, and a minimum dimension of the blank region is greater than a diameter of the first data pin.

Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.

A semiconductor package includes a base substrate, a first semiconductor chip, a second semiconductor chip, a first voltage bonding wire, a second voltage bonding wire and a first capacitance-sharing bonding wire. The base substrate includes substrate pads. The first semiconductor chip is stacked on the base substrate in a vertical direction and includes first chip pads. The second semiconductor chip is stacked on the first semiconductor chip in the vertical direction and includes second chip pads. The first voltage bonding wire electrically connects a first substrate voltage pad of the substrate pads and a first chip voltage pad of the first chip pads. The second voltage bonding wire electrically connects a second substrate voltage pad of the substrate pads and a second chip voltage pad of the second chip pads. The first capacitance-sharing bonding wire electrically connects the first chip voltage pad and the second chip voltage pad.

Interposers for semiconductor packages including photonic components, such as an optical waveguide and/or an integrated circuit (IC) photonic die, integrated into the interposer. The interposer includes a substrate, a redistribution structure over the substrate, where the redistribution structure includes a plurality of conductive features in a dielectric material, and an optical waveguide located over and/or within the substrate. The optical waveguide includes a core material surrounded by a cladding material, where the core material has an index of refraction that is greater than an index of refraction of the cladding material, and the optical waveguide is configured to transmit optical signals through the interposer to and/or from an IC photonic die electrically coupled to an IC electronic die that provides an interface between electronic and photonic components of the semiconductor package. In various embodiments, improved data transport bandwidth and energy efficiency in the semiconductor package may be provided.

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. For example, a semiconductor device may include: a substrate; an interposer at least partially on a first surface of the substrate that faces in a first direction; a first semiconductor chip on a first surface of the interposer that faces in the first direction; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction that crosses the first direction; a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip that faces in the first direction or at least partially on a first surface of the second semiconductor chip that faces in the first direction, wherein the hybrid diamond thermal interposer includes diamond particles within a metal.

Methods, systems, and devices for interposers for double-sided memory bonding are described. A semiconductor system may implement stacks of memory dies on two sides of an interposer. For example, one or more first stacks of memory dies may be bonded to the interposer on a first side, and one or more second stacks of memory dies may be bonded to the interposer on a second side of the interposer opposite the first side. In some implementations, a processor may also be bonded to the interposer on the first side. As such, the semiconductor system may implement additional stacks of memory dies without being limited by a height of the stack, while supporting a heat sink to be bonded with a surface of the one or more first stacks of memory dies and a surface of the processor.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.