A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.

A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

A semiconductor device has a carrier. A first redistribution layer is formed over the carrier. A capping layer is formed on the first redistribution layer. The capping layer includes an anti-reflective coating. An insulating layer is formed on the capping layer. An opening is formed through the insulating layer using photolithography. A conductive layer is formed in the opening.

A package structure and a semiconductor structure are provided. A ball grid array is disposed on a surface of a package substrate in the package structure, and the ball grid array includes multiple data ball grids. In a second direction, a maximum of two data ball grids are allowed to be consecutively arranged. The second direction is a row extension direction of the ball grid array.

Provided are a memory chip, a chip stacked structure, and a memory. For the memory chip, n via groups in a first region are symmetrical to n via groups in a second region with respect to a first axis, n via groups in a third region are symmetrical to n via groups in a fourth region with respect to the first axis, and the n via groups in the first region are symmetrical to the n via groups in the fourth region with respect to a second axis. For each via group, a first via is symmetrical to a second via with respect to a third axis, a third via is symmetrical to a fourth via with respect to the third axis, and the first via is symmetrical to the fourth via with respect to a fourth axis.

Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).