According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.

A stacked electronic device is disclosed. The stacked electronic device can comprise a first stacked assembly including a first plurality of integrated device dies. The first plurality of integrated device dies can comprise a first integrated device die. A second stacked assembly is disposed over the first stacked assembly. The second stacked assembly includes a second plurality of device dies, and the second plurality of device dies can comprise a second integrated device die. A first channel can extend at least partially through the first stacked assembly. The first integrated device die can comprise a first circuit, and the first channel is connected to the first circuit. A second channel can extend through and bypass the first stacked assembly, the second channel extending at least partially through the second stacked assembly. The second integrated device die can comprise a second circuit, and the second channel is connected to the second circuit.

A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.