A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

A substrate for a SIP is that has a portion of its top surface covered with spaced apart electrically conductive landing pads for electrical connection to components located on the surface and the landing pads serve as interconnection pads for making electrical connections between at least a portion of said pads when interconnected by a segment of bond wire to form at least a portion of the SIP. Methods for use of the universal substrate in SIP system design and manufacture of a SIP.

Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.

A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.

A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

A semiconductor device manufacturing method includes forming a first film containing a first device on a first substrate, forming a second film containing a semiconductor layer on a second substrate, and changing the semiconductor layer into a porous layer. The method further includes forming a third film containing a second device on the second film, and bonding the first substrate and the second substrate to sandwich the first film, the third film, and the second film therebetween. The method further includes separating the first substrate and the second substrate from each other at a position of the second film.

A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.