An operating method for a non-volatile memory device includes; performing a read operation on adjacent memory cells connected to an adjacent word line proximate to a target word line to determine adjacent data, classifying target memory cells connected to the target word line into groups according to the adjacent data, setting a read voltage level for each of the groups by searching for a read voltage level for target memory cells in at least one of the groups, and performing a read operation on target memory cells using the read voltage level set for each of the groups.

A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

Disclosed is a semiconductor device comprising a substrate including a cell array region and a connection region, an electrode structure extending in a first direction on the substrate and including vertically stacked electrodes having pad sections arranged stepwise on the connection region, a first contact plug connected to a first one of the pad sections, a pair of first vertical structures that penetrate the first one of the pad sections and are spaced apart from each other in a first direction by a first distance, a second contact plug connected to a second one of the pad section and having a vertical length that is greater than that of the first contact plug, and a pair of second vertical structures that penetrate the second one of the pad sections and are spaced apart from each other in the first direction by a second distance that is greater than the first distance.

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.

According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.

In an example, a method for forming a three-dimensional (3D) memory device is disclosed. A semiconductor layer is formed. A memory stack on the semiconductor is formed. A channel structure extending through the memory stack and the semiconductor layer is formed. An end of the channel structure abutting the semiconductor layer is exposed. A portion of the channel structure abutting the semiconductor layer is replaced with a semiconductor plug.