A power convertor including an inverter driving a motor generator, a first DC/DC converter connected to a DC bus of the inverter, a second DC/DC converter varying voltage of the DC bus, and a control device controlling the inverter, the first DC/DC converter, and the second DC/DC converter. The power converter is a power conversion device setting voltage of the DC bus in a second control state higher than a voltage of the DC bus in a first control state by controlling the second DC/DC converter according to the control device. By setting the voltage of the DC bus of the inverter to a low voltage when it is not necessary, it is possible to reduce loss in the inverter and the step-down DC/DC converter, and to downsize the inverter and the step-down DC/DC converter.

A DC-to-DC voltage converter includes a converter input for receiving a DC voltage. A first switch is coupled between the input and a first node. A second switch is coupled between the first node and a ground. An inductor is coupled between the first node and a converter output. A capacitor is coupled between the converter output and ground. An output voltage synthesizer is coupled to the converter input and the converter output for synthesizing the voltage at the first node and for generating a control signal for at least one of the first switch and the second switch in response to the voltages at the converter input and the converter output.

A control circuit and a control method for a power converter are provided. The power converter includes a plurality of resonant tanks and a plurality of switches disposed between an input terminal and an output terminal. The switches correspond to a first mode and a second mode, respectively, and the control circuit includes a first switch control circuit, a first zero current detection circuit, a second zero current detection circuit, a first switch off detector, a modulation time calculation module, a second switch control circuit, a third zero current detection circuit, a fourth zero current detection circuit, and a second switch off detector. The control circuit uses a plurality of zero current detection circuits to perform time modulations on a plurality of rectifier switches in the switches.

A power supply circuit includes: an output terminal for supplying power for a semiconductor device at the terminal; a control circuit configured to control a power level of the supplied power based on a control signal; and an input for receiving one or more timing signals, wherein the power supply circuit is configured to derive an indication for a scheduled change of a load current of the supplied power using the one or more timing signals. The power supply circuit is configured to adapt the control signal based on the indication for the scheduled change of the load current.

The invention relates to a choke circuit and a bus power supply incorporating same. Such a coil choke circuit includes an inductor connected between a first input terminal and a first output terminal, a boost circuit connected between a second input terminal and a second output terminal for increasing the voltage level that is output by the second output terminal. A switching element is connected in parallel to the boost circuit for bypassing the boost circuit. Additionally, a comparator is connected between the first input terminal and the first output terminal for detecting a potential difference across the inductor; wherein in case the comparator detects a potential difference higher than a threshold, the switching element is controlled to be in an OFF state; and in case the comparator detects a potential difference lower than or equal to the threshold, the switching element is controlled to be in an ON state.

A switching converter has a self-driven bipolar junction transistor (BJT) synchronous rectifier. The BJT rectifier includes a BJT and a parallel-connected diode, and has a low forward voltage drop. In a first portion of a switching cycle, a main switch is on and the BJT rectifier is off. Current flows from an input, through the main switch, through the first inductor, to an output. Current also flows through the main switch, through the second inductor, to the output. In a second portion of the cycle, the main switch is turned off but the inductor currents continue to flow. Current flows from a ground node, through the BJT rectifier, through the first inductor, to the output. The BJT is on due to the second inductor drawing a base current from the BJT. In one example, the main switch is a split-source NFET that conducts separate currents through the two inductors.

A novel integrated rectifier and boost converter circuit architecture is disclosed. The rectifier architecture includes a plurality of identical half-bridge rectifiers connected to receiving antennas to convert wireless AC power into DC power. The integrated rectifier may be coupled in series with a charging inductor in a boost converter. The inductor may discharge upon operation of two micro-controller-driven switching transistors using predetermined threshold and timing scheme to turn on/off. The rectifier architecture may provide high power densities, improve efficiency at larger load currents, and may be enabled in an integrated circuit with eight RF signal inputs, eight half-bridge rectifiers, and eight DC outputs ganged together as single feed into the boost converter. The rectifier circuit topology may include a comparator driven by the boost controller with a proprietary algorithm which suits control for a maximum power point tracking functionality, and an external micro-controller for additional control of the boost converter.

A controller for a switching regulator receiving an input voltage and generating a regulated output voltage includes a buck control circuit and a boost control circuit. The controller activates the buck control circuit to generate the regulated output voltage having a first voltage value less than the input voltage. The controller activates the boost control circuit to return charges stored on the output capacitor at the output node to the input node, thereby driving the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command instructing the controller to allow the output voltage to decay, the controller operates in the boost mode using the boost control circuit to recycle the stored charge at the output node while ramping down the output voltage.

A power stage for a DC-to-DC voltage converter includes a voltage input, a high-side n-channel transistor, a high-side p-channel transistor, and a low-side n-channel transistor. The voltage input is couplable to a supply voltage. The drain terminal of the high-side n-channel transistor is coupled to the voltage input and the source terminal is coupled to a first node that is couplable to an output stage of the DC-to-DC converter. The source terminal of the high-side p-channel transistor is coupled to the voltage input and the drain terminal is coupled to the first node. The drain terminal of the low-side n-channel transistor is coupled to the first node and the source terminal is coupled to a ground.

The present invention introduces a new compact Voltage Regulator Module (VRM) solution that hybrids a buck converter with a resonant switched-capacitor auxiliary circuit that is connected at the load side. By using a new control concept of the present invention, the auxiliary circuit effectively mimics increased capacitance during loading and unloading transient events, reducing the burden on both the input and output filters, and reduces the current stress.