An apparatus and method for a buck converter and regulation loop with pulse skipping modulation (PSM) and auto-transition to pulse frequency modulation (PFM) comprising of a peak current loop configured to provide a method of generating a constant minimal inductor peak current, a system configured to provide a method of skipping pulses utilizing a pulse skipping modulation (PSM) mode of operation, and, the peak current loop configured to provide a method of auto-transition from the pulse skipping modulation (PSM) to a pulse frequency modulation (PFM) mode of operation.

A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.

A multiple-output DC-DC converter has a first and a second DC-DC sub-converter, each DC-DC subconverter may be a buck, boost, or buck-boost converter having a primary energy-storage inductor. Each DC-DC subconverter drives a separate output of the multiple-output converter and typically has a separate feedback control circuit for controlling output voltage and/or current. The converter has a common timing circuit to maintain a phase offset between the first and DC-DC subconverters. The primary energy storage inductors of the first and second DC-DC converter are magnetically coupled to raise an effective ripple frequency of the converter and simplify output filtering.

A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.

A switched mode power supply (100) comprises a reactive element (10) and a control signal generator (30) is arranged to generate a first control signal at a first output (31) of the control signal generator (30) and a second control signal at a second output (32) of the control signal generator (30). The first output (31) of the control signal generator (30) is coupled to a first input (21) of a switching stage (20) by means of a first control signal path (40) and the second output (32) of the control signal generator (30) is coupled to a second input (22) of the switching stage (20) by means of a second control signal path (50). The switching stage (20) is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element (10) by coupling it alternately to first and second supply voltages. A delay detector (60) is arranged to generate a delay indicator signal indicative of a relative delay between the first control signal at the first input (21) of the switching stage (20) and the second control signal at the second input (22) of the switching stage (20). An adjustable delay stage (53) in one of the first and second signal paths (40, 50) is arranged to, responsive to the delay indicator signal, control an adjustable delay so that a first delay experienced by the first control signal passing from the first output (31) of the control signal generator (30) to the first input (21) of the switching stage (20) is substantially equal to a second delay experienced by the second control signal passing from the second output (32) of the control signal generator (30) to the second input (22) of the switching stage (20).

A method may include operating a DC-DC switch converter in a forced continuous conduction mode in which for each switching cycle of the switch converter during the forced continuous conduction mode, the switch converter operates in a series of phases including: a first phase in which an inductor current flowing in an inductor of the switch converter increases from zero to a controlled positive current magnitude with respect to a first terminal and a second terminal of the inductor; a second phase in which the inductor current decreases from the controlled positive current magnitude to approximately zero; a third phase in which the inductor current decreases from approximately zero to a controlled negative current magnitude with respect to a first terminal and a second terminal of the inductor; and a fourth phase in which the inductor current increases from the controlled negative current magnitude to approximately zero.

A switching regulator includes circuitry for reducing conductive emissions caused when the regulators switch from one transistor switch to the other. The switching regulator includes at least one switch with a diode connected from the source to the drain of at least one of the transistor switches. When the regulator switches from one transistor switch to the other, the circuitry initiates turning on the switch with a relatively small, current-limited signal, waits for the diode across the recently turned off switch to complete reverse recovery, and then quickly turns the new switch fully on.

The present disclosure relates to a switching power converter, a control circuit and an integrated circuit therefor, and a constant-current control method. The control circuit samples a valley value of an electric current through a first power transistor in a power stage circuit and a peak value of an electric current through a second power transistor in the power stage circuit, and obtains parameters representing an output current in accordance with an average value of the valley value and peak value. Thus, the constant-current control can be performed by sampling the electric current through the first power transistor and the second power transistor. Moreover, the switching power converter simplifies a current feedback loop for outputting a constant current, and the integrated circuit has fewer pins.

An electronic device includes first and second transistors coupled in series between first and second source voltage levels. An inductor is coupled between a node coupling the first and second transistors and a load. Control logic is operative to generate control pulses operative to switch the first and second transistors. The controller generates the control pulses as a continuous stream of control pulses in a continuous conduction mode, and skips generation of some control pulses in a discontinuous conduction mode in response to a pulse skipping signal. A pulse skipping circuit is operative to generate a sense voltage as a function of an inductor current in the inductor, compare the sense voltage to ground, and generate a pulse skipping signal to the control logic when the sense voltage is below ground.

A single inductor positive and negative voltage output device, which not only reduces a chip area, but also meets mutual independent application needs of positive and negative voltage output load currents, which includes an inductor L, one end of the inductor L is connected to the drain of a first PMOS power switch M1 and to the drain of a third NMOS power switch M3 respectively, the other end of the inductor L is connected to the drain of a second NMOS power switch M2 and to the source of a fourth PMOS power switch M4 respectively, the gates of M1, M2, M3 and M4 are respectively connected to a drive circuit (1), the source of M1 is connected to a power supply terminal VIN, the source of M2 is connected to a ground terminal (6), the source of M3 is connected to a negative voltage output end VON, the drain of M4 is connected to a positive voltage output end VOP, the negative voltage output end VON is connected to ground terminal by a negative terminal capacitor CON, the positive voltage output end VOP is connected to ground terminal by a positive terminal capacitor COP, the positive voltage output end VOP by a positive terminal feedback circuit and the negative voltage output end VON by a negative terminal feedback are respectively connected to the drive circuit (1) by a logic control circuit (15).