A control circuit includes a timeout circuit configured to receive a first control signal. The timeout circuit asserts a timeout output signal on a timeout circuit output responsive to an expiration of a time period following assertion of the first control signal. A counter circuit has an input coupled to the timeout circuit output and has a counter circuit output. Responsive to assertion of the first control signal, the counter circuit selectively increments an output count value on the counter circuit output responsive to the timeout output signal having a first logic state or decrements the output count value on the counter circuit output responsive to the timeout output signal having a second logic state. A comparator circuit has a control input coupled to the counter circuit output. The comparator circuit adjusts a magnitude of a reference signal responsive to the output count value from the counter circuit.

A deadtime control scheme for improving buck converter light load efficiency.

A current detection circuit for detecting a current in a Switch Mode Power Supply (SMPS) having a first switch and a second switch coupled in series and an output filter including an inductor and a capacitor coupled to a switch node formed by the first and second switches, has a current sensing circuit for sensing a current across the second switch and generating a current sensing signal indicating current information of the second switch, and a current emulation circuit for emulating current information of the first switch. The current emulation circuit includes an inductance sensing circuit for acquiring a real-time rate of change in inductor current and an AC emulation circuit for computing the AC portion of the current information of the first switch based on the real-time rate of change in inductor current.

A voltage converter controller, adapted to a voltage converter circuit, includes a power switch controller and a dead-time determining circuit. The power switch controller receives a PWM signal and outputs a high-side control signal and a low-side control signal accordingly to control the conduction and cut-off of a high-side power switch and a low-side power switch respectively. When the power switch controller starts to control the low-side power switch cut-off, after a first dead-time, the power switch controller starts to control the high-side power switch conducting. The dead-time determining circuit detects a current of the low-side power switch to be larger or smaller than a threshold current when the low-side power switch is conducted, and determines the first dead-time to be a first value or a second value accordingly.

The present invention provides, in one aspect, a restart timer that turns a switching element ON when it is not possible to turn the switching element ON via a zero-current detection and frequency reduction part, and specifically includes: a frequency reduction part that reduces a switching frequency of the switching element by delaying the turn-ON timing of the switching element by the zero-current detection and frequency reduction part when a light load state is detected; and a timer adjustment part that lengthens the restart time of the restart timer by synchronizing with the turn-ON timing of the switching element that was delayed by the frequency reduction part.

Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of T.sub.pp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay T.sub.delay after the pre-pulse switch has been opened.

In accordance with embodiments of the present disclosure, systems and methods may include an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The systems and methods may also include a predriver circuit coupled to the input and a gate terminal of the first switch device, the predriver circuit configured to drive an input voltage signal to the gate terminal of the first switch device and configured to select an effective impedance of the gate terminal of the first switch device based on the input.

The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.

A voltage converter includes a switching driver, a controller, a low-pass filter and a pulse width modulation signal generator. The switching driver includes a pull-up switching circuit connecting an input voltage to a switching node in response to a pull-up signal and a pull-down switching circuit connecting a ground voltage to the switching node in response to a pull-down signal. The controller generates the pull-up signal and the pull-down signal in response to a pulse width modulation signal and measures pull-up and pull-down turn-on times of the pull-up and pull-down switching circuits in real time to control a dead time. The low-pass filter filters a switching voltage signal on the switching node to generate an output voltage. The pulse width modulation signal generator generates the pulse width modulation signal based on a reference signal and the output voltage.

Methods and systems for connecting a photovoltaic module and an inverter having an input capacitor are presented. The photovoltaic system includes a maximum power point tracking (MPPT) controller coupled between the inverter and the photovoltaic module. The MPPT controller includes a direct current (DC) converter configured to reduce, in a forward buck mode, a voltage of the photovoltaic module, to supply power from the photovoltaic module to the input capacitor of the inverter. The photovoltaic system also includes a microcontroller unit (MCU) configured to control the DC converter to allow the photovoltaic module to operate at a maximum power point, and to increase, in a reverse boost mode, a voltage of the input capacitor of the inverter, to dissipate power from the input capacitor in the photovoltaic module, and the MPPT controller is configured to, based upon one or more triggers.